Design and Implementation of low power and High speed multiplier using Quaternary carry look - Ahead adder.
Abstract
In this project, we will be discussing about Need of
Digital Signal Processing (DSP) systems which is
embedded and portable has been increasing as a
result of the speed growth of semiconductor
technology. Multiplier is a most crucial part in
almost every DSP application. So, the low power,
high speed multipliers is needed for high speed DSP.
Array multiplier is one of the fast multiplier because
it has regular structure and it can be designed very
easily. Array multiplier is used for multiplication of
unsigned numbers by using full adders and half
adders. It depends on the previous computations of
partial sum to produce the final output. Hence, delay
is more to produce the output. In the previous work,
Complementary Metal Oxide Semiconductor
(CMOS) Carry Look-ahead Adders (CLA) and
CMOS power gating based CLA are used for
maximizing the speed of the multiplier and to
improve the power dissipation with minimum delay.
CMOS logic is based on radix 2(binary) number
system. In arithmetic operation, major issue
corresponds to carry in binary number system.
Higher radix number system like Quaternary Signed
Digit (QSD) can be used for performing arithmetic
operations without carry. The proposed system
designed an array multiplier with Quaternary Signed
Digit number system (QSD) based Carry Look
Ahead Adder (CLA) to improve the performance.
Generally, the quaternary devices require simpler
circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve
the speed of adder and high throughput. In array
multiplier architecture, instead of full adders, carry
look-ahead adder based on QSD are used. This
facilitates low consumption of power and quick
multiplication. Tanner EDA tool is used for
simulating the proposed multiplier circuit in 180 nm
technology. With respect to area, Power Delay
Product (PDP), Average power proposed QSD CLA
multiplier is compared with Power gating CLA and
CLA multiplier
Downloads
References
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Books Referred :
1. M. M. Mano, Digital Design with an Introduction to
the Verilog HDL. Pearson.
2. K. L. Kishore and N. S. Sivanandam, VLSI Design
Techniques for Analog and Digital Circuits. Pearson.
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