Design and Validation of High Performance SRAM with High Recoverability of Multinode Soft Error

Abstract

With the advancement of technology, the size of 
transistors and the distance between them are 
reducing rapidly. Therefore, the critical charge of 
sensitive nodes is reducing, making SRAM cells, used 
for aerospace applications, more vulnerable to soft
error. If a radiation particle strikes a sensitive node 
of the standard 6T SRAM cell, the stored data in the 
cell are flipped, causing a single-event upset (SEU). 
Therefore, in this paper, a Soft-Error-Aware 
ReadStability- Enhanced Low Power 12T (SARP12T) 
SRAM cell is proposed to mitigate SEUs. To analyze 
the relative performance of SARP12T, it is compared 
with other recently published soft-error- aware 
SRAM cells. All the sensitive nodes of SARP12T can 
regain their data even if the node values are flipped 
due to a radiation strike. To estimate the proposed 
LP10T SRAM cell’s performance, it is compared 
with some state-of-the-art SRAM cells using HSPICE 
in 16-nm CMOS predictive technology model 
Furthermore, SARP12T can recover from the effect 
of single event multi-node upsets (SEMNUs) induced 
at 
its storage node pair. Along with these 
advantages, the proposed cell exhibits the highest 
read stability, as the ‘0’storing storage node, which 
is directly accessed by the bit line during read 
operation, can recover from any upset. Furthermore, 
SARP12T consumes the least hold power. SARP12T 
also exhibits higher write ability and shorter write 
delay than most of the comparison cells. All these 
improvements in the proposed cell are obtained by  

exhibiting only a slightly longer read delay and  
consuming slightly higher read and write energy.