A DFT Compatible In-Situ Timing Error Detection and Correction Structure
Abstract
In-situ timing error detection and correction (EDAC)
structure is widely adopted in timing-error resilient
circuits to reduce the conservative timing guard
band induced by process, voltage, and temperature
(PVT) variations. However, it introduces the latch-
based data-path as well as extra detection and
propagation logic, therefore challenges the design
for-testability (DFT) implementation. In this article,
we propose a novel DFTcompatible EDAC structure
with significant signal control simplification and
test- pattern complexity reduction, featuring low area
and test overhead. This structure leverages a new
scannable EDAC cell (SEDC) which can be
configured for timing EDAC in normal mode, or for
shift operations as a flip-flop in scan mode.
Specifically, the proposed detection logic can be
controlled succinctly in scan shift operations and
then observed via the global error propagation logic
with simple control signal configurations during the
test.
The performance of the full adder would impact the
whole system. Full Adder Cell plays an important
role
in Digital Signal Processors (DSPs),
Application
Specific
ICs
(ASICs),
and
microprocessors, etc. Fault categorized into three
categories permanent, transient or intermittent. Due
to the presence of electromagnetic noises, cosmic
rays, crosstalk and power supply noises, transient
fault takes place. The system leads to failure and
when the faults exist on a system than stop delivering
the desired results. In the practical system, it is impossible to create a perfect system, so fault
tolerant is essential. When faults are present in a
system and system is capable of performing its
desired function continuously that’s called the fault
tolerant. Fault- tolerant design is used to attain a
reliability or availability which cannot be obtained
by its counterpart the faultintolerant design.
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