Accuracy Configurable Adder for Approximate Arithmetic Designs
Abstract
The Accuracy-Configurable Approximate (ACA)
Adder introduces a novel hardware design that
addresses the growing demand for energy-efficient
and high-performance computing in modern
applications. Unlike traditional arithmetic units,
which lack dynamic accuracy adjustment, the ACA
Adder seamlessly integrates approximate and
accurate
computation modes with runtime
configurability, enabling real-time adaptation to
varying precision requirements. By leveraging a
parameterized sub-adder architecture and an error
detection and correction mechanism, the ACA Adder
achieves a remarkable 97% pass rate in approximate
mode while maintaining full accuracy in critical
computations. Experimental validation using
Gaussian Smoothing demonstrates the ACA Adder's
practical efficacy. In approximate mode, the design
achieves a Peak Signal-to-Noise Ratio (PSNR) of
33.13 dB and a Structural Similarity Index (SSIM) of
0.8611, delivering high-quality results with
significant energy savings. In accurate mode, the
ACA Adder achieves a PSNR of 39.90 dB and an
SSIM of 0.9663, ensuring precision for critical
computations. The design achieves up to 37% power
savings and a 24.6% throughput improvement
compared to conventional adders, making it an ideal
solution for energy-constrained applications such as
multimedia processing, signal processing, and
embedded systems. By striking an optimal balance
between performance, energy efficiency, and
computational accuracy, the ACA Adder sets a new standard for next-generation integrated circuits,
enabling smarter and more sustainable hardware
designs.
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References
1. Kulkarni, P., Gupta, P., and Ercegovac, M.,
“Trading Accuracy for Power with an
Underdesigned Multiplier Architecture,” VLSI
Design, 2011.
2. Lu, S.-L., “Speeding Up Processing with
Approximation Circuits,” IEEE Computer,
2004.
3. Zhu, N., et al., “Design of Low-Power High
Speed Truncation-Error-Tolerant Adder and Its
Application in Digital Signal Processing,”
IEEE Trans. VLSI Systems, 2010.
4. Shin, D., and Gupta, S. K., “A Re-Design
Technique for Datapath Modules in Error
Tolerant Applications,” Proc. Asian Test
Symp., 2008.
5. Verma, A. K., Brisk, P., and Ienne, P.,
“Variable Latency Speculative Addition: A
New Paradigm for Arithmetic Circuit Design,”
Proc. DATE, 2008.
6. George, J., Marr, B., Akgul, B. E. S., and
Palem, K. V., “Probabilistic Arithmetic and
EnergyEfficient Embedded Signal Processing,”
CASES, 2006.
7. Hanif, M. A., Khan, A. H., and Gill, S. S.,
“Energy-Aware
Approximate
Arithmetic
Circuits for Low-Power Computing,” IEEE
Transactions on Circuits and Systems I, vol. 63,
no. 5, pp. 1231– 1242, 2015.
8. Zhang, T., and Zhao, W., “Accuracy
Configurable Arithmetic Units for High
Efficiency
Embedded Systems,” IEEE
Embedded Systems Letters, vol. 9, no. 4, pp.
120–123, 2017.
9. George, J., et al., “Low-Power Configurable
Approximate
Adders
for
Edge-AI
Applications,” IEEE Transactions on VLSI
Systems, vol. 27, no. 8, pp. 1593–1604, 2018.
10. Liu, C., Shi, Q., and Schulte, M., “Design and
Analysis of Accuracy-Aware Approximate
Adders,” IEEE Transactions on Emerging
Topics in Computing, vol. 7, no. 1, pp. 92–105,
2019.
Transactions on Computers, vol. 69, no. 3, pp.
489–501, 2021.
13. Agarwal, S., Gupta, P., and Kumar, R.,
“Energy-Quality Scalable Adders for Next
Generation IoT Devices,” IEEE Internet of
Things Journal, vol. 8, no. 2, pp. 987–995,
2021.
14. Bose, A., Althoff, M., and Kim, Y., “Design
and Validation of Accuracy-Configurable
Adders for Edge Devices,” Proc. DATE, 2022.
15. Chen, J., and Wang, Z., “A Hybrid
Approximate Adder for AI Inference on Low
Power Platforms,” IEEE Journal of Solid-State
Circuits, vol. 58, no. 1, pp. 156–168, 2023.
16. Gupta, M., and Garg, R., “Application-Driven
Accuracy Configurable Adders for Adaptive
Workloads,” IEEE Access, vol. 11, pp. 28456
28468, 2023.
17. Lin, H., and Zhang, Y., “Deep Learning
Accelerators with Configurable Approximate
Arithmetic Units,” IEEE Transactions on AI
and Machine Learning, vol. 3, no. 2, pp. 189
201, 2024.
18. Chen, Y., et al., “Performance Analysis of
Accuracy Configurable Adders in Image
Processing,”
IEEE
Transactions
on
Multimedia, vol. 26, pp. 785–797, 2024.
19. "Xilinx Vivado Installation Instructions,"
11. Singh, R., and Palem, K., “Reconfigurable
Approximate Adders for High-Performance
DSP Systems,” Proc. ISCAS, 2020.
12. Shafique, N., and Henkel, J., “Dynamically
Adaptive Approximate Computing for Energy
Efficient
Embedded
Transactions on Computers, vol. 69, no. 3, pp.
489–501, 2021.
13. Agarwal, S., Gupta, P., and Kumar, R.,
“Energy-Quality Scalable Adders for Next
Generation IoT Devices,” IEEE Internet of
Things Journal, vol. 8, no. 2, pp. 987–995,
2021.
14. Bose, A., Althoff, M., and Kim, Y., “Design
and Validation of Accuracy-Configurable
Adders for Edge Devices,” Proc. DATE, 2022.
15. Chen, J., and Wang, Z., “A Hybrid
Approximate Adder for AI Inference on Low
Power Platforms,” IEEE Journal of Solid-State
Circuits, vol. 58, no. 1, pp. 156–168, 2023.
16. Gupta, M., and Garg, R., “Application-Driven
Accuracy Configurable Adders for Adaptive
Workloads,” IEEE Access, vol. 11, pp. 28456
28468, 2023.
17. Lin, H., and Zhang, Y., “Deep Learning
Accelerators with Configurable Approximate
Arithmetic Units,” IEEE Transactions on AI
and Machine Learning, vol. 3, no. 2, pp. 189
201, 2024.
18. Chen, Y., et al., “Performance Analysis of
Accuracy Configurable Adders in Image
Processing,”
IEEE
Transactions
on
Multimedia, vol. 26, pp. 785–797, 2024.
19. "Xilinx Vivado Installation Instructions,"
20.
MathWorks,
"Installation
of
MATLAB and Simulink," 2014. [Online].
Available: https://www.mathworks.com.
