Synchronous Up Counter with CMOS Clock-Gated Control, Compact Toggle Flip-Flop, and Fast Local Clock Generation
Abstract
The clock signal in a counter consumes one-third of the total power. The number of switching actions is minimized in this study to decrease power consumption. The counter's power consumption was reduced even further by decreasing the power consumption of the flip-flops. Combining TSPCL (True Single Phase Clock Logic (TSPCL) with SVL (Self-Controllable Voltage Level) may accomplish this. The Flip-Flop operation is performed by TSPCL at a fast speed and low power. The SVL approach reduces the complexity of the system by suppressing the power generated by leakage current and using fewer transistors. The new design uses low percent less energy than the current one. The suggested technique identifies potential applications for low-power contemporary electronics. To validate proposed design using Cadence virtuoso 45nm Technology. Tool have been used.
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References
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