Design Of A Low-Latency Pipelined Fir Filter Through Advanced Critical Path Analysis
Keywords:
FIR filter, FFA, EKG, DSP, WRT, PP, Carry adder.Abstract
A filter with a finite period impulse response that settles to zero in a finite amount of time is known as a FIR in digital signal processing. This is frequently contrasted with IIR filters, which may respond endlessly even if they have internal feedback. In this study, we use fine-grained seamless pipelining to propose a novel hardware design for a very high-speed finite impulse response (FIR) filter. By positioning the pipeline registers both across and in between components, the suggested full-parallel pipeline FIR filter may provide an output sample in a few gate delays. Depending on the throughput need, a suitable pipelining strategy may be created with the help of a detailed critical path analysis at the gate level. Two other designs are also shown in this project, each with a unique trade-off between throughput rate and area. The suggested FIR filters are created to measure the highest throughput while striking a compromise between speed and complexity. Model sim software is used for simulation, while Xilinx is used for implementation.
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