Optimizing Cmos Multiplexer Layout Design And Implementation Across Multiple Technologies

Abstract

There are several subfields of engineering that
are dependent on multiplexer circuits, which are essential
pieces of equipment. A reduction in the amount of time and
effort required for design is the objective of very large-scale
integration (VLSI) research. With the use of CMOS logic,
the purpose of this article is to outline the procedures that
must be taken in order to construct a 2-to-1 multiplexer,
which will ultimately result in a circuit that is more effective
and less complicated. In this article, a wide variety of design
ideas are used in order to reduce the effect, complexity, and
power consumption of the multiplexer. Specifically, the
technology that operates at a wavelength of 35 nm is
investigated in this research. In conclusion, we focus our
attention to enhancing the effective area of the multiplexer
by conducting an analysis of the design processes
themselves.