ANALYZING THE PERFORMANCE OF A HYBRID 1-BIT FULL ADDER CIRCUIT WITH LOW POWER CONSUMPTION AND HIGH SPEED

Abstract

In this endeavor, across a variety of 1-cycle, full snake setups using both comparing metal-oxidesemiconductor
(CMOS) reasoning and transmission entryway reasoning is represented. The arrangement was
first completed for 1 cycle and thereafter loosened up for 32 digits besides. The circuit was completed using
Cadence Virtuoso contraptions in 180-and 90-nm advancement. Execution limits like power, deferral, and
configuration district were differentiated and the current plans, for instance, comparing pass-semiconductor
reasoning, transmission entrance snake, transmission work snake, creamer pass-reasoning with static CMOS
yield drive full snake, and so forth For 1.8-V stock at 180-nm advancement, the ordinary power usage (4.1563
μW) was seen as amazingly low with humbly low deferral (224 ps) coming about as a result of the deliberate
wire of incredibly fragile CMOS inverters joined with strong transmission entryways. Looking at potential gains
of the comparable were 1.17664 μW and 91.3 ps at 90-nm development working at 1.2-V stock voltage. In
relationship with the current full snake designs, the current execution was found to offer basic improvement to
the extent that power and speed.