DESIGN OF REVERSIBLE DECODER WITH MOS TRANSISTORS FOR LOW-POWER AND FAULT TOLERANCE

Abstract

The approach adopted for this design centers around reversible logic synthesis, specifically tailored for
the creation of an n-to-2n decoder, with 'n' signifying the quantity of data bits. In this context, the circuitry is
exclusively structured utilizing reversible, fault-tolerant Fredkin and Feynman double gates. Consequently, the entire
system inherently possesses fault tolerance as an integral feature. Furthermore, the paper encompasses an algorithm
devised for the purpose of crafting this generalized decoder, ensuring versatility in its applicability. Additionally, the
study introduces several lower bounds pertaining to constant inputs, garbage outputs, and the quantum cost
associated with the reversible, fault-tolerant decoder. The comparative analysis undertaken reveals the superiority of
the proposed design across various dimensions, including quantum cost, delay, hardware complexity, and scalability,
significantly outperforming existing methodologies.