PULSEREG: A NOVEL SHIFT REGISTER DESIGN WITH PULSED LATCHES FOR ENHANCED POWER AND AREA EFFICIENCY

Abstract

This project proposes a novel and energy-efficient approach for implementing a low-power and areaefficient
shift register using beat snares. By incorporating beat locks to override flip-flops, the proposed design
minimizes both the area footprint and energy consumption. Unlike traditional systems that rely on a single beat
clock signal, this approach utilizes a range of nand on-overlapping delayed beat clock signals to address timing
issues between beat locks. By distributing the snares among a small number of sub-shifter enlistees and employing
temporary storage locks, the move register significantly reduces the dependency on beat clock signals. To construct
a 256-cycle move register with beat locks, a 0.18m CMOS process with VDD = 1.8V was employed. The
implementation occupied an optimized area of 6600 sq. ft. At a clock frequency of 100 MHz, the power
consumption was measured to be 1.2mW. Comparative analysis demonstrated that the suggested move register
could potentially save up to 37% of the required area and 44% of the required power compared to a conventional
move register built with flip-flops. A move register is a circuit comprised of interconnected flip-flops, all driven by a
common clock signal. Each flip-flop's output is connected to the "data" input of the subsequent flip-flop in the
sequence. This arrangement enables the circuit to shift the stored "piece display" by one position on every clock
edge, introducing new data at its input and releasing the last piece in the sequence. In a broader context, a move
register can have multiple dimensions, where both the input data and output stages consist of bit arrays. This can be
achieved by employing multiple move registers with the same bit length in parallel.