Develop An 8-4 And 9-4 Compressor That Is Optimized For High-Speed Multiplication

Abstract

This research aims to develop stateof-
the-art compressors optimized for efficient
high-speed multiplication. The proposed
compressors have two advantages: reduced
latency and increased space usage. In contrast,
lower-order compressors have a little larger
Energy Delay Product (EDP). Something like
this has to be thought about. Using the
sophisticated compressors that have been
provided, this study aims to evaluate the
performance of 8×8, 16×16, and 24×24
multipliers. Furthermore, the research contrasts
these multipliers with the standard lower-order
compressors. The results suggest that the
recently designed compressors are well-suited to
tasks requiring rapid multiplication. We used a
Cadence RTL Compiler to model these
compressors, simulating conditions like a 25 °C
temperature and a 1.2 volt supply voltage.