Comprehensive Analysis Of Low Power Consumption And High-Speed Performance In A Hybrid 1-Bit Full Adder Circuit For Efficient Digital Processing

Abstract

study investigates various configurations of 1-cycle full adder designs, leveraging both
complementary metal-oxide-semiconductor (CMOS) logic and transmission gate logic to achieve high
performance. The initial focus was on developing a 1-cycle operational model, which was subsequently scaled
to a 32-bit architecture to assess scalability and performance under broader computational requirements. The
circuit designs were implemented and analyzed using Cadence Virtuoso, a leading design tool, across two
prominent technology nodes: 180 nanometers and 90 nanometers. The research places a strong emphasis on
evaluating key performance metrics, including power consumption, propagation delay, and design area. These
metrics were benchmarked against existing full adder designs, such as those based on complementary passtransistor
logic, transmission gate snake logic, transmission function snake logic, and hybrid pass-logic
architectures combined with static CMOS output drivers. By systematically comparing these configurations, the
study aimed to identify designs offering optimal trade-offs between power efficiency, speed, and resource
utilization. For the 180-nanometer technology node, the full adder design demonstrated exceptional
performance at a supply voltage of 1.8 V. The average power consumption was recorded at an impressively low
value of 4.1563 μW, while maintaining a minimal delay of 224 ps. This efficiency was achieved through the
strategic use of highly sensitive CMOS inverter networks, carefully optimized for low power, and robust
transmission gates, ensuring reliable signal integrity and minimal energy dissipation. In the case of the more
advanced 90-nanometer technology node, operating at a reduced supply voltage of 1.2 V, the design achieved
even greater efficiency. The power consumption was significantly reduced to 1.17664 μW, and the propagation
delay was minimized to just 91.3 ps. These results underscore the potential of scaling down to smaller
technology nodes to achieve higher speed and lower energy requirements. When compared to existing full adder
designs, the proposed configurations demonstrated considerable improvements in power efficiency and
computational speed. The innovative use of hybrid logic elements, combined with a meticulous design approach,
enabled the study to surpass the benchmarks set by traditional designs. These advancements highlight the
relevance of optimizing logic gate configurations to address the ever-increasing demands for energy-efficient
and high-performance digital systems. This research not only contributes valuable insights into full adder design but also provides a solid foundation for future work aimed at further optimizing arithmetic circuits for a
wide range of applications in digital electronics and integrated circuit design.